The present invention relates to the deposition of dielectric layers, and more specifically to a method and apparatus for forming a dielectric layer such as a borophosphosilicate glass (BPSG) layer, having improved film uniformity, superior gap fill/reflow capability, and smoother surface morphology. In addition to resulting in a higher deposition rate, the method of the present invention forms the dielectric layer in a manner that produces substantially less downstream residue than conventional methods. The method reduces the frequency of reactor cleaning to increase throughput of processed wafers. The present invention is particularly useful when forming a dielectric layer used as a premetal dielectric (PMD) layer, but may also be applied to the formation of intermetal dielectric (IMD) layers, passivation layers, and other layers.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film, for example, an oxide of silicon, on a semiconductor substrate. Silicon oxide is widely used as an insulating layer in the manufacture of semiconductor devices. A silicon oxide film can be deposited by thermal chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) processes from a reaction of silane (SiH4), tetraethylorthosilicate (Si(OC2H5)4, hereinafter referred to as xe2x80x9cTEOSxe2x80x9d) or a similar silicon source, with an oxygen source such as O2, ozone (O3), or the like. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. PECVD processes promote excitation and/or disassociation of the reactant gases by the application of radio frequency energy to a reaction zone proximate the substrate surface, thereby creating a plasma of highly-reactive species to produce the desired film.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two-year/half-size rule (often called xe2x80x9cMoore""s Lawxe2x80x9d) which means that the number of devices that fit on a chip doubles every two years. Wafer fabrication plants today are routinely producing devices with 0.5 xcexcm and even 0.35 xcexcm size features. Tomorrow""s plants soon will be producing devices having even smaller geometries. As device sizes become smaller and integration density increases, issues that were not previously considered important by the industry are becoming of paramount concern.
One particular use for a silicon oxide film is as a separation layer between the polysilicon gate/interconnect layer and the first metal contact layer for MOS transistor connections. Such separation layers are referred to as premetal dielectric (PMD) layers because they are typically deposited before any of the metal layers in a multilevel metal structure. In addition to having a low dielectric constant, low stress, good gettering capability, and good adhesion properties, it is important for PMD layers to have good planarization characteristics or be compatible with planarization techniques. When used as a PMD layer, the silicon oxide film is deposited over a lower level polysilicon gate/interconnect layer that usually contains raised or stepped surfaces. The initially deposited film generally conforms to the topography of the poly layer and is typically planarized before an overlying metal layer is deposited. A standard reflow process, in which the oxide film is heated to a temperature at which it flows, may be used to planarize the film. With small device dimensions, it is critical in some processes that reflow of PMD layers and other process steps be carried out below 800xc2x0 C. to maintain shallow junctions and prevent the degradation of self-aligned titanium silicide contact structures or the like. As an alternative to reflow, a chemical mechanical polishing (CMP) or etching technique may be used.
Because of its low dielectric constant, low stress, good adhesion properties, good gettering capability, and capability to reflow at high temperatures, boron phosphorus silicate glass (BPSG) is one silicon oxide film that has found particular applicability in PMD layers. Standard BPSG films are formed by introducing phosphorus and boron sources into a processing chamber along with the silicon and oxygen sources normally required to form a silicon oxide layer. Examples of phosphorus sources include triethylphosphate (TEPO), triethylphosphite (TEPi), trimethylphosphate (TMOP), trimethylphosphite (TMPi), and similar compounds. Examples of boron sources include triethylborate (TEB), trimethylborate (TMB), diborane (B2H6) and similar compounds. Deposition techniques include atmospheric pressure CVD (APCVD), sub-atmospheric pressure CVD (SACVD), low pressure CVD (LPCVD), and plasma enhanced CVD (PECVD). Most semiconductor manufacturers utilize SiH4-based BPSG films to reflow at high temperatures ( greater than 900xc2x0 C.) for 0.5 xcexcm and greater device geometries. At geometries less than 0.5 xcexcm, stringent thermal budget and gap fill requirements necessitate the use of chemistries such as TEOS/O3 which provide films of excellent gap fill and reflow capability. For example, TEOS/O3-based BPSG films produced by APCVD or SACVD using nitrogen carrier gas can be reflowed at greater than 900xc2x0 C. or subjected to a rapid thermal process and CMP to achieve gap fill and planarization. Conventional BPSG processes, especially APCVD, use nitrogen (N2) as the carrier gas to transport vaporized liquid sources, like the TEOS, TEB, and TEPO, into the chamber.
BPSG films at a 2-6 weight percent (wt %) boron concentration and a 2-9 wt % phosphorus concentration are often used for reflow. At these concentration levels, the reflow temperature of known BPSG films formed using nitrogen carrier gas with TEOS/O3 is generally greater than about 850xc2x0 C. With conventional BPSG processes using a nitrogen carrier gas, BPSG films can be produced which flow at temperatures below 850xc2x0 C. by increasing the concentration of boron to 4.5 wt % or higher. The stability of the BPSG layer, however, is adversely affected at such increased boron concentrations.
Conventional BPSG processes using nitrogen as a carrier gas in forming silicon oxide layers often encounter problems in fabricating smaller geometry devices, such as filling closely-spaced gaps on semiconductor structures. These processes using nitrogen carrier gas result in as-deposited step coverage that is not optimal, and therefore require higher temperatures to achieve gap fill and planarization requirements. That is, conventional BPSG processes using nitrogen as the carrier gas result in reflow temperatures over 850xc2x0 C., which are often too high for tighter thermal budgets.
The use of helium as the carrier gas in other processes has been mentioned previously, with some even experimenting with its use in BPSG processes. However, the industry has relied primarily on nitrogen as the carrier gas in the BPSG process, mainly because nitrogen is cheaper than helium. Also, the industry did not recognize helium carrier gas as having benefits that outweigh the advantage of nitrogen""s reduced cost.
With growing pressure on manufacturers to improve efficiency, another problem is the need for frequent system maintenance procedures to clean the reactor system by removing the residue formed after the repeated processing of hundreds of wafers. During CVD processing, deposition gases released inside a processing chamber form a thin BPSG layer on the surface of a substrate being processed. Unwanted oxide deposition occurs elsewhere in the reactor, for example, on areas such as the walls of the processing chamber during such CVD processes. In closed vacuum systems, some of the undeposited gas molecules are pumped out of the chamber, along with partially reacted compounds and reaction by-products, through a vacuum line, commonly referred to as the xe2x80x9cforeline.xe2x80x9d Many of the compounds in this exhausted gas are still in highly reactive states and/or contain residues or particulate matter that can form unwanted deposits in the foreline, as well as in various parts of the chamber including, for example, the area between the gas box and gas distribution plate. In open nonvacuum systems such as APCVD systems, undesired oxide residue is deposited on the entire exhaust channel. Failure to clean the residue from the reactor and exhaust channels often results in degraded, unreliable processes and defective wafers. Without frequent cleaning procedures, the residue particulates built up in the reactor and exhaust can migrate onto the wafer. The problem of particulates causing damage to the devices on the wafer is of particular concern with today""s increasingly small device dimensions.
Thus, system maintenance is important for the smooth operation of wafer processing, as well as resulting in improved wafer yield and better product performance. Typically, two types of cleaning procedures are possible. The first cleaning procedure uses an etchant gas, optionally formed with a plasma, to remove residue from chamber walls and other areas. The first cleaning procedure is performed without opening the chamber. Commonly performed between deposition steps for every wafer or every n wafers, this first cleaning procedure adequately cleans the chamber walls, but residue often remains in the foreline and other areas of the chamber. To clean the foreline and these other areas adequately, the duration of the cleaning operation may be increased, but this adversely affects wafer throughput.
The second cleaning procedure involves opening the chamber system and physically wiping the entire reactor, including the foreline (for a vacuum system), exhaust, and other areas having accumulated residue, with a special cloth and cleaning fluids. This second cleaning procedure, often referred to as a preventive maintenance cleaning, is time-consuming because the chamber must be opened and manually cleaned. Occurring periodically during the processing of wafers, the preventive maintenance cleaning operation is performed less often than the first cleaning procedure. Preventive maintenance cleaning constitutes a serious, albeit necessary, interruption in the manufacturing of wafers. The frequent preventive maintenance cleanings associated with conventional processes using nitrogen as the carrier gas impact the continuous production of wafers in the manufacturing line. It is desirable to increase the number of wafers between each time-consuming maintenance procedure. This reduces total unproductive time and increases the total number of wafers produced.
From the above, it can be seen that an oxide film having good gap fill and stability after lower temperature reflows is desirable. It can also be seen that a method and apparatus for forming an oxide film that allows processing as many high quality wafers as possible, without the need for frequent chamber maintenance, while minimizing undesirable residues formed during processing such wafers is desirable.
The present invention addresses the above problems of the prior art by providing a method and related apparatus for forming a dielectric layer having good gap fill capability, stability, and low reflow temperature with less frequently required chamber cleaning procedures. In particular, the method and apparatus relate to forming a dielectric layer, such as BPSG, of high quality, while obtaining additional previously unknown and unexpected benefits in the manufacturing process.
The present invention involves the use of helium instead of nitrogen as carrier gas in a process for forming a dielectric layer such as BPSG to provide various unexpected benefits. According to one embodiment, the present invention provides a method for forming a dielectric film on a substrate. The use of helium produces substantially less downstream and upstream residue than a process using nitrogen. The method includes introducing process gas containing silicon, oxygen, and first dopant atoms into the chamber; using helium as the carrier gas in the system; and processing more substrates between cleanings than a process using nitrogen as carrier gas. A further advantage of the invention is that the dielectric films formed on the substrates may be subsequently annealed to achieve gap fill and planarization at a lower temperature than with films formed by the same process using nitrogen as carrier gas.
The present method may be performed in a substrate processing system. The system includes a housing for forming a chamber; a susceptor, located within the housing, for holding a substrate; a gas distribution manifold, located within the housing and situated substantially parallel to the susceptor, for introducing process gases into the chamber. The system also includes a gas mixing chamber, coupled to the gas distribution manifold, into which a first plurality of gases are introduced using a helium carrier gas to form the process gases; and a source distribution system, coupled to the gas mixing chamber, for introducing the first plurality of gases into the gas mixing chamber, the source distribution system including a source of helium carrier gas. Additionally, the system includes a heater for heating the substrate, and a processor for controlling the source distribution system and the heater. The system further includes a memory coupled to the processor and storing a program for directing the operation of the CVD reactor system. The program is responsive to a user input to stop processing a straight run of substrates in order to perform a cleaning, where the user input is not used for an accumulated deposited film thickness greater than 350 xcexcm.